As Internet and information technology have continued developing, the necessity for fast packet processing in computer networks has also grown in importance. All emerging network applications require deep packet classification as well as security-related processing and they should be run at line rates.
Hence, network speed and the complexity of network applications will continue increasing and future network processors should simultaneously meet two requirements: high performance and high programmability. We will show that the performance of single processors will not be sufficient to support future demands. Instead, we will have to turn to multicore processors, which can exploit the parallelism in network workloads.
In this paper, we focus on the cache coherence protocols which are central to the design of multicore-based network processors. We investigate the effects of two main categories of various cache coherence protocols with several network workloads on multicore processors. Our simulation results show that token protocols have a significantly higher performance than directory protocols. With an 8-core configuration, a token protocol improves the performance compared to directory protocols by a factor of nearly 4 on average. Importance of Coherence Protocols with Network Applications on Multicore Processors
This trend translated in a need for ever more powerful network processors since applications will continue demanding even faster processing of incoming packets and requiring more powerful computing platforms dedicated to the processing of packets. Therefore, using high-performance microprocessors as a dedicated resource for network applications such as QoS, URL matching, virus detection, intrusion detection, and load balancing require deep packet classification processing and security- related processing which is more computation intensive than any other network applications. While all these network applications should be running at line rates, most programmable network processors on the market today aim at relatively low performance. However, the general trend in microprocessor design has been to embed an increasing number of cores in processor chips rather than the traditional approach of increasing the clock frequency to improve the performance.
As messages travel through the Internet, the intermediate routers process incoming packets for operations such as packet decoding, packet encoding, packet forwarding, etc. The processing speed of those operations becomes a crucial factor if we are to meet today’s high network speeds. In order to avoid making packet processing part of the bottleneck of computer communications, network processors have been developed: they are programmable processing units specifically intended to assist in the abovementioned operations. The multiple cores are integrated on a single chip, the individual cores often share a cache. If multiple processors share a cache, two different processors can have different values for the same location of the memory space, resulting in a cache coherence problem. A cache system is said to be coherent if any read of a memory location returns the most recently written value of that data element.